Why RISC-V for FRISC OS

FRISC OS targets RISC-V because it is open, simple, and extensible. But let me explain exactly what that means and why it matters for a Lateralus-native operating system.

◉ The Problem with x86 and ARM

x86 is a 45-year-old architecture buried under layers of backward compatibility. Variable-length instructions. Dozens of addressing modes. A segment register system that made sense in 1978 but is now vestigial baggage.

ARM is better designed, but it's proprietary. Want to build ARM chips? Pay ARM Holdings. Want to extend the ISA? Ask permission. Want to see the full specification? Sign an NDA.

For an open-source OS written in an open-source language, closed ISAs feel wrong.

◉ Open ISA

RISC-V is BSD-licensed. You can:

• Read the complete specification (freely available PDFs)
• Implement your own CPU without paying royalties
• Add custom instructions for your domain
• Simulate everything in open-source tools like Spike

No black boxes. No licensing negotiations. No NDAs. Just open documentation and open implementations.

◉ Clean Design

RISC-V was designed in 2010, learning from decades of ISA mistakes:

Fixed instruction width: All base instructions are 32 bits. Fetching, decoding, and pipelining are trivial compared to x86's variable-width nightmare.

Regular encoding: Source registers are always in the same bit positions. The decoder can extract operands before it even knows the instruction type.

Simple privilege levels: Machine, Supervisor, User. No rings 0-3, no SMM mode, no TrustZone complexity.

No condition codes: Branch instructions compare registers directly. No implicit flags register to track.

// x86: set flags, then branch on flags
cmp eax, 0
jz  label

// RISC-V: branch compares directly
beqz a0, label

◉ Extensibility

RISC-V has a modular extension system:

Extension	Purpose
I	Base integer (required)
M	Multiply/Divide
A	Atomics
F	Single-precision float
D	Double-precision float
C	Compressed (16-bit) instructions
V	Vector operations

FRISC OS targets RV64GC — that's RV64 (64-bit) with IMAFD (integer, multiply, atomics, float, double) and C (compressed). A practical general-purpose configuration.

◉ Hardware Availability

In 2024, real RISC-V hardware is finally practical:

• HiFive Unmatched: Quad-core SiFive U74 at 1.2 GHz, 16GB RAM, PCIe. Real desktop-class Linux performance.
• StarFive VisionFive 2: Quad-core JH7110, $65. The "Raspberry Pi of RISC-V."
• QEMU: Full-system emulation for development without hardware.
• Milk-V Mars: Another quad-core JH7110 board, even cheaper.

We develop FRISC primarily in QEMU, then test on VisionFive 2 boards. The HiFive Unmatched is the "production" target.

◉ Lateralus ↔ RISC-V Synergy

Lateralus's C99 backend generates clean, predictable code that RISC-V handles beautifully:

// Lateralus pipeline
data |> transform |> filter |> reduce

// Maps naturally to RISC-V calling convention:
// Arguments in a0-a7, return in a0
// No complex ABI to wrestle with

RISC-V's simplicity means the generated code is fast without complex backend optimizations. What you write is close to what runs.

◉ The Future is Open

We believe RISC-V will win the long game:

• China is investing heavily (domestic chip independence)
• European Union has RISC-V in its chip strategy
• Google is using RISC-V in its TPUs
• Qualcomm, NVIDIA, and Western Digital all have RISC-V projects

By building on RISC-V now, FRISC OS will be ready when open hardware becomes ubiquitous.

◉ Getting Started

Want to try FRISC on RISC-V? Start with QEMU:

# Build FRISC kernel
lateralus build --target riscv64 kernel/

# Run in QEMU
qemu-system-riscv64 -machine virt -bios none \
    -kernel build/frisc.elf -serial stdio

See the OS page for full documentation on building and running FRISC.